The present invention relates to a method and/or architecture for content-addressable memories generally and, more particularly, to a method and/or architecture for a content-addressable memory with cascaded match, read and write logic in a programmable logic device.
A type of memory commonly used in many types of switching circuits is a content-addressable memory (CAM). Compared to a random access memory, a content-addressable memory (CAM) has a unique method of accessing data words within the memory. In a random access memory, during a read operation, an address is supplied that uniquely identifies one location within the memory. The memory responds with a data word stored in the addressed memory location.
In a content-addressable memory, each stored word consists of two sets of bits: tag bits and data bits. During a read operation of a content-addressable memory, a set of tag bits is supplied. The tag bits supplied are compared to the tag bits stored in every memory location simultaneously. If the supplied tag bits match the tag bits stored in any of the memory locations, the memory array presents an indication that a match has occurred. Once a match has occurred, the tag and data bits in the matching memory word can be read.
Content-addressable memory have been included in programmable logic devices (PLDs). However, conventional content-addressable memories restrict a memory word to a single tag and data width. For many applications, the single tag and data width are not sufficient. In particular, many applications can require tag or data widths that are much wider than are currently available.
One example of a conventional PLD with a CAM can be found in the Altera(copyright) APEX(trademark) family of devices (APEX 20K Programmable Logic Device Family Data Sheet, Altera Corp., March 2000, Ver. 2.06). The Altera(copyright) APEX(trademark) family of programmable logic devices contain memory blocks, called embedded system blocks (ESB). Each of the embedded system blocks can be configured as a content-addressable memory. When used as a CAM, each block can store 32 words of 32 bits each.
The content-addressable memory blocks in the Altera(copyright) APEX(trademark) PLD architecture cannot be combined to implement larger tag widths. The inability to implement larger tag widths is a serious drawback. Many data communications applications require larger tag widths than can be supported by the Altera(copyright) APEX(trademark) PLD architecture. For those applications, the Altera(copyright) APEX(trademark) PLD architecture will not function effectively.
The Altera(copyright) APEX(trademark) PLD CAM blocks can be combined to implement wider data widths. However, doing so leads to a very inefficient use of the memory bits. When the CAM blocks are combined to implement wider data widths, all the tag bits must be duplicated in each block. Since the number of memory blocks can be limited, the inefficient use of memory can cause the Altera(copyright) APEX(trademark) PLD CAM blocks to be unusable for many applications that require wide data widths.
Content-addressable memories can be useful in data communication applications. Different data communication protocols have different sizes for source and destination addresses. For example, supporting Ethernet, ATM, SONET, and any other protocols can require different tag and data widths. A programmable logic device with content-addressable memories having arbitrarily adjustable tag and data widths would be desirable.
The present invention concerns a programmable logic device comprising one or more memory blocks. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a content-addressable memory with cascaded match, read and write logic in a programmable logic device that may (i) provide arbitrary tag and data widths, (ii) require little storage overhead, (iii) indicate the start of a new tag using a single storage bit per memory word, and/or (iv) allow a user to efficiently implement wider content-addressable memories.